10.14489/td.2026.11.pp.004-014

2026, 11 November

DOI: 0.14489/td.2026.11.pp.004-014

Kuznetsov V. V., Andreev V. V., Artemiev B. V., Vlasov A. I.
STUDY OF THE RESISTANCE OF MDP IONIZING RADIATION DETECTORS TO THE EFFECTS OF STATIC ELECTRICITY
(pp. 4-14)

Abstract. Electrostatic discharge protection of semiconductor circuits manufactured using complementary metal-insulator-semiconductor technology is a pressing issue. The classic protection option is a circuit comprising a protective element (a diode or a field-effect transistor with a grounded gate) and auxiliary components (diffusion and polysilicon resistors). The resistance of semiconductor circuits to electrostatic discharge can be assessed using a transmission line pulse model, which can be converted to a human body model. Circuit simulation of ESD protection circuits allows for the identification of weak points in protection early in the development process, thereby reducing the number of tests. However, most SPICE models of semiconductor components do not account for the effects that occur under ESD pulse conditions: the thyristor effect and the nonlinear dependence of conductor resistance at high currents. Therefore, further development of models that take these effects into account is necessary.

Keywords: MIS detector, ionizing radiation, static electricity, model.

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V. V. Kuznetsov, V. V. Andreev, B. V. Artemiev, A. I. Vlasov (Federal State Autonomous Educational Institution of Higher Education “Bauman Moscow State Technical University (National Research University)”, Moscow, Russia) E-mail: Данный адрес e-mail защищен от спам-ботов, Вам необходимо включить Javascript для его просмотра. , Данный адрес e-mail защищен от спам-ботов, Вам необходимо включить Javascript для его просмотра. , Данный адрес e-mail защищен от спам-ботов, Вам необходимо включить Javascript для его просмотра. , Данный адрес e-mail защищен от спам-ботов, Вам необходимо включить Javascript для его просмотра.

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1. Kuznetsov, V. V., & Andreev, V. V. (2024). ESD induced irreversible degradation processes in the semiconductor devices. In 6th International Youth Conference on Radio Electronics, Electrical and Power Engineering (REEPE) (5 p.). Moscow, Russian Federation.
2. Puvvada, V., Srinivasan, V., & Gupta, V. (2000). A scalable analytical model for the ESD N-well resistor. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (pp. 437–445). Anaheim, CA, USA.
3. Parikh, C. D., & Patrikar, R. M. (1999). A compact model for the N-well resistor. Solid-State Electronics, 43(3), 683–685.
4. Notermans, G. (1997). On the use of n-well resistors for uniform triggering of ESD protection elements. In Proceedings Electrical Overstress / Electrostatic Discharge Symposium (pp. 221–229). Santa Clara, CA, USA.
5. Boselli, G. (2001). On high injection mechanisms in semiconductor devices under ESD conditions. University of Twente.
6. Krieger, G., & Niles, P. (1989). Diffused resistors characteristics at high current density levels – analysis and applications. IEEE Transactions on Electron Devices, 36(2), 416–423.
7. Barth, J. E., Verhaege, K., Henry, L. G., & Richner, J. T. (2001). TLP calibration, correlation, standards, and new techniques. IEEE Transactions on Electronics Packaging Manufacturing, 24(2), 99–108.
8. Kuznetsov, V. V., & Andreev, V. V. (2024). Transmission line pulse setup for electrostatic discharge robustness testing of the semiconductor devices. Instruments and Experimental Techniques, 67(2), 268–273.
9. Scholz, M., Linten, D., Sangameswaran, S., et al. (2009). ESD on-wafer characterization: Is TLP still the right measurement tool? IEEE Transactions on Instrumentation and Measurement, 58(10), 3418–3426.
10. Pan, Z., Li, C., Hao, W., Li, X., & Wang, A. (2022). ESD protection designs: Topical overview and perspective. IEEE Transactions on Device and Materials Reliability, 22(3), 356–370.
11. Andreev, D. V., Andreev, V. V., Konuhova, M., & Popov, A. I. (2024). Technique of high-field electron injection for wafer-level testing of gate dielectrics of MIS devices. Technologies, 12, 102–112.
12. Andreev, D. V., Maslovsky, V. M., Andreev, V. V., & Stolyarov, A. A. (2022). Modified ramped current stress technique for monitoring thin dielectrics reliability and charge degradation. Physica Status Solidi A, 219(9), 2100400–2100405.
13. Caruso, A., Spirito, P., & Vitale, G. (1974). Negative resistance induced by avalanche injection in bulk semiconductors. IEEE Transactions on Electron Devices, 21(9), 578–586.
14. Brinson, M., & Kuznetsov, V. V. (2016). Qucs-0.0.19S: A new open-source circuit simulator and its application for hardware design. In 2016 International Siberian Conference on Control and Communications (SIBCON) (5 p.). Moscow, Russia.
15. Grabinski, W., Brinson, M., Nenzi, P., et al. (2014). Open-source circuit simulation tools for RF compact semiconductor device modelling. International Journal of Numerical Modelling, 27, 761–779.
16. Chukhraev, I. V., & Drach, V. E. (2023). Parameter optimization of broadband interference-suppressing filters of high-performance power supplies. In 5th International Youth Conference on Radio Electronics, Electrical and Power Engineering (REEPE) (5 p.). Moscow, Russian Federation.
17. Brinson, M., & Kuznetsov, V. V. (2017). Improvements in Qucs-S equation-defined modelling of semiconductor devices and IC’s. In 2017 MIXDES – 24th International Conference “Mixed Design” of Integrated Circuits and Systems (pp. 137–142). Bydgoszcz, Poland.
18. Brinson, M. E., & Kuznetsov, V. V. (2017). Extended behavioural device modelling and circuit simulation with Qucs-S. International Journal of Electronics, 105, 412–425.
19. Kuznetsov, V. V., Andreev, V. V., & Lomakin, S. A. (2025). Electrostatic discharge protection devices macromodelling using open-source tools. Proceedings of the Institute for System Programming of the RAS, 37(3), 121–130. [in Russian language].
20. Tenbroek, B. M., Lee, M. S. L., Redman-White, W., et al. (1996). Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques. IEEE Transactions on Electron Devices, 43(12), 2240–2248.
21. Staniloiu, M.-F., Popescu, H.-S., Rezmerita, G., et al. (2022). Spice model of a real zener diode tested at room temperature. In International Conference and Exposition on Electrical and Power Engineering (EPE) (pp. 182–186). IEEE.
22. Zhou, Y. P., Ding, G., & Hajjar, J.-J. (2019). ESD protection impact and modelling of bias-dependent series resistance in diodes. In 41st Annual EOS/ESD Symposium, Vol. EOS-41 (7 p.).
23. Vashchenko, V., Martynov, Y., & Sinkevitch, V. (1997). Electrical instability and filamentation in ggMOS protection structures. Solid-State Electronics, 41(11), 1761–1767.

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